1. Field of the Invention
The present invention relates to a digital-to-analog converter and related control method, and more specifically, to a digital-to-analog converter and related method with ones complement current supply structure for simplifying control logic.
2. Description of the Prior Art
Digital-to-analog converters are a common and important structure in the modern electrical circuits. Generally speaking, digital data is much easier to be processed, saved and calculated. When presenting digital data, a digital-to-analog converter is needed to transform the digital data into an analog signal. For instance, a digital microprocessor is used in the control system for controlling the speed of a compact disk driven by a motor or how much power to supply to the pick-up head to write data to the compact disk. However, the digital data of the microprocessor first needs to be transformed to an analog signal by a digital-to-analog converter for controlling the motor rotation or controlling the power of the pick-up head.
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art digital-to-analog converter 10. The example in FIG. 1 is a four-bit digital-to-analog converter. The converter 10 receives a four-bit input code 26 and provides an output voltage Vp as an analog output, the output voltage Vp corresponding to the input code 26. The four-bit input code 26 comprises bits Ap3 to Ap0, the bit Ap3 being the most significant bit, the bit Ap0 being the least significant bit. The converter 10 comprises a control logic 12 and an electrical module 14. The input code 26 is transformed to a plurality of positive control bits Yp0 to Yp2, negative control bits Xp0 to Xp2 and Co. The electrical module 14 provides a bias voltage by a direct current source Vcc and comprises a positive electrical module 16A formed by a plurality of positive current sources 18A to 18C, a negative electrical module 16B formed by a plurality of negative current sources 20A to 20C, a negative current source 20D, a OP amp 24, and a resistance R. Each positive and negative current source is electrically connected to a node Na through a switch 22, and the resistance Rp is electrically connected between the node Na and the output node Nb of the OP amp 24. By the virtual ground at the node Na of the OP amp24, the current flows through the resistance Rp for setting up the output voltage Vp. In the electrical module 14, different positive and negative current sources provide different currents. The switch 22 is controlled by a corresponding positive control bit or negative control bit for providing a corresponding current to the node Na. As shown in FIG. 1, the negative current sources 20A to 20C provide the negative currents of 1I, 2I, 4I and 8I (the current I is a constant) according to ascending powers of two, the switches of the negative current sources being controlled by the negative control bits Xp0 to Xp2 and Co. The positive current sources 18A to 18C provide the positive currents of 1I, 2I, 4I and 8I similarly, the switches of the positive current sources being controlled by the positive control bits Yp0 to Yp2. For instance, if the negative control bit is 1, the corresponding switch 22 is connected to the node Na, enabling the negative current source to provide a negative current of 1I to the node Na. On the contrary, if the negative control bit is 0, the corresponding switch 22 is off, stopping the negative current source from providing a negative current of 1I to the node Na. In other words, controlling the positive and negative control bits to be 0 or 1 controls the positive and negative current sources to be connected or not connected to the node Na for controlling the current flowing through the resistance Rp and for controlling the magnitude of the corresponding output voltage. The control logic 12 of the converter 10 encodes the input code as the positive and negative control codes to control the output voltage Vp generated by the electrical module 14 according to the input code 26.
Please refer to FIG. 2 (also refer to FIG. 1). FIG. 2 is a table 30 of the relationship between the input code 26, the output voltage Vp and the positive and negative control bits. For instance, as shown in the table 30, when the input code 26 (bits Ap3 to Ap0) is xe2x80x9c0001xe2x80x9d, the converter 10 provides the output voltage Vp=1*I*Rp (abbreviated as 1IRp). When the input code 26 is xe2x80x9c0110xe2x80x9d, the output voltage will be 6IRp, and so on. In other words, the input code 26 represents a special value in binary, and the converter 10 provides an output voltage Vp with a direct proportion to the special value. As mentioned above, xe2x80x9c0001xe2x80x9d represents xe2x80x9c1xe2x80x9d and xe2x80x9c0110xe2x80x9d represents xe2x80x9c6xe2x80x9d. The converter 10 provides the corresponding voltages 1IRp and 6IRp. In digital arithmetic, a negative value is marked by 2s complement. Therefore, when the converter 10 receives the input code 26 in 2s complement, the converter 10 will provide a corresponding output voltage Vp. As shown in FIG. 2, when the input code 26 is xe2x80x9c1111xe2x80x9d, it represents xe2x80x9cxe2x88x921xe2x80x9d by 2s complement, the converter 10 providing a negative voltage 1IRp. When the input code 26 is xe2x80x9c1011xe2x80x9d, it represents xe2x80x9cxe2x88x925xe2x80x9d by 2s complement, the converter 10 providing a negative voltage 5IRp.
In order to establish the relationship between the input code and the output voltage in FIG. 2, the converter uses the positive and negative control bits to control the output voltage, connecting or not connecting the positive and negative current sources with the node Na. For instance, when the input code 26 is xe2x80x9c0110xe2x80x9d, the output voltage Vp is 6IRp, the positive control bits Yp2 to Yp1 being xe2x80x9c1xe2x80x9d, the positive current sources 18B and 18C separately providing 2I and 4I positive current to the node Na. There should be a 6IRp output voltage through the resistance Rp. At the same time, the other positive bit Yp0 and the negative control bits Xp2 to Xp0 and Co are xe2x80x9c0xe2x80x9d for preventing the corresponding current sources from providing current to the node Na. Also, when the input code 26 is xe2x80x9c1011xe2x80x9d, the output voltage Vp is 5IRp, the positive control bits Yp0 to Yp2 being xe2x80x9c0xe2x80x9d, the negative control bits Xp2 to Xp0 and Co respectively being xe2x80x9c1xe2x80x9d,xe2x80x9c0xe2x80x9d,xe2x80x9c1xe2x80x9d, and xe2x80x9c0xe2x80x9d. The current sources 20C and 20A of the electrical module 14 separately provide negative current 4I and 1I to the node Na for establishing the output voltage Vp through the resistance Rp.
As shown in FIG. 2, when indicating negative values by 2s complement, the most significant bit Ap3 of the input code 26 is a sign code. When the input code 26 represents a positive value or zero, the bit Ap3 is xe2x80x9c0xe2x80x9d. When the input code 26 represents negative value by 2s complement, the bit Ap3 is xe2x80x9c1xe2x80x9d. A value code 32 is formed by the other bits Ap2 to Ap0 of the input code 26, the bits Ap2 and Ap0 respectively being the most and least significant bits. When the input code 26 represents a positive value, the value can be represented by Ap2*(2^2)+Ap1*(2^1)+Ap0*(2^0). Note that the positive current sources 18C to 18A in FIG. 1 respectively provide 4I((2^2)I), 2I, and 1I current. Therefore, when the input code represents a positive value, the positive control bits Yp2 to Tp0 are respectively equal to the bits Ap2 to Ap0 (the negative control bits Yp2 to Yp0 and Co are xe2x80x9c0xe2x80x9d) for controlling the total current at the node Na to be in direct proportion to the value of the value code 32, the total current provided by the positive current sources 18A to 18C, and the corresponding output voltage. The positive control bits Yp2 and Yp0 are respectively the most and least significant bits. A positive control code 28A is formed by the control bits Yp2 to Yp0.
As shown in FIG. 1, the negative current sources 20A to 20C respectively correspond to the positive current sources 18A to 18C, providing a magnitude of negative current the same as that of the positive current and a phase of the negative current opposite that of the positive current. The negative control bits Xp2 to Xp0 can correspond to the positive control code 28A. A negative control code 28B is formed by the negative control bits Xp2 to Xp0, the negative control bits Xp2 and Xp0 being respectively the most and least significant bits. Due to the negative current sources 20A to 20C corresponding to the positive current sources 18A to 18C, the magnitude of the negative output voltage Vp provided by the negative current sources according to the negative code 28B is the same as that of the positive output voltage Vp provided by the positive current sources according to the positive code 28A and the phase of the negative output voltage Vp is opposite that of the positive output voltage Vp. As shown in FIG. 2, when the positive control code 28A is xe2x80x9c110xe2x80x9d (the negative control code 28B is xe2x80x9c000xe2x80x9d), the positive output voltage Vp is 6IRp. When the negative control code 28B is xe2x80x9c110xe2x80x9d (the positive control code is xe2x80x9c000xe2x80x9d), the negative output voltage is 6IRp. In the converter 10 in FIG. 1, when the value code 32 of the input code 26 represents a positive value, the positive control code 28A should be the same as the value code 32 to provide a correct and corresponding output voltage Vp. When providing the same magnitude of a negative output voltage Vp, the negative control code 28B should be the same as the positive control code. It can be inferred that when the prior art converter 10 provides a negative output voltage Vp, the negative control code 28 is the same as the value code 32 that generates the same magnitude of the positive output voltage Vp. For instance, when the value code 32 is xe2x80x9c101xe2x80x9d, the converter 10 provides a 5IRp positive output voltage Vp. When the negative control code 28B is xe2x80x9c101xe2x80x9d (the positive control code 28A is xe2x80x9c000xe2x80x9d), the converter 10 provides a xe2x88x925IRp negative output voltage Vp.
However, when the value code 32 of the input code 26 represents a negative value by 2s complement of a positive value, the converter 10 generates the corresponding negative control code 28B to provide a negative output voltage Vp according to the value code 32, the value code 32 representing the negative value and the negative control code 28B being 2s complement. For instance, when the value code 32 is xe2x80x9c011xe2x80x9d representing 5, the negative control code 28B is xe2x80x9c101xe2x80x9d representing 5 to force the converter 10 to provide a 5IRp negative output voltage Vp. When the value code 32 is xe2x80x9c001xe2x80x9d representing 7 by 2s complement, the negative control code is xe2x80x9c111xe2x80x9d representing 7 to provide a 7IRp negative output voltage Vp.
As mentioned above, the control logic 12 needs many logic gates to transform the input code 26 into the corresponding positive and negative control code. Please refer to FIG. 3 (also refer to FIGS. 1 and 2). FIG. 3 is a diagram of the control logic circuit 12 of the converter 10. The control logic 12 comprises a plurality of AND gates 36, inverters 34, and half-adders 39A to 39C. Each half-adder 39A to 39C comprises an AND gate 36 and a XOR gate 38. The two inputs of each half-adder 39A to 39C are respectively the two inputs of the AND gate 36 and the XOR gate 38 and the outputs of the half-adder are the outputs of the XOR gate 38 and the AND gate 36, wherein the output of the XOR gate 38 is connected with a sum node S and the output of the AND gate 36 is connected with a carry node C for inputting the two inputs of the sum node S and the carry node C. When the two inputs of the half-adder are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, the sum node S being xe2x80x9c1xe2x80x9d, the carry node C being xe2x80x9c0xe2x80x9d, this means that xe2x80x9c0xe2x80x9d+xe2x80x9c1xe2x80x9d equals to xe2x80x9c1xe2x80x9d. When the two inputs are the same (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d), the sum node S is always xe2x80x9c0xe2x80x9d and the carry node C is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d respectively. This means that xe2x80x9c0xe2x80x9d+xe2x80x9c0xe2x80x9d equals to xe2x80x9c0xe2x80x9d and that xe2x80x9c0xe2x80x9d+xe2x80x9c1xe2x80x9d equals to xe2x80x9c10xe2x80x9d in binary. As shown in FIG. 3, in the half-adders 39A to 39C, one of the two inputs of a latter half-adder is electrically connected to the carry node C of the former half-adder and the other is used to invert a bit of the value code when the sign code Ap3 is xe2x80x9c1xe2x80x9d. For instance, one of the inputs of the half-adder 39B receives the input from the carry node C of the half-adder 39A and the other is used to receive an input of the inverter of the bit Ap1 when the sign code Ap3 is xe2x80x9c1xe2x80x9d. When the sign code Ap3 is xe2x80x9c1xe2x80x9d, one of the two inputs of the first half-adder 39A receives the input of the inverter 34 of the bit Ap0, and the other receives an input xe2x80x9c1xe2x80x9d at the same time. As mentioned above, the connection of each half-adder 39A to 39C is to invert the bits Ap0 to Ap2 of the value code 32 for generating an input code (the inverter 34 of the bit Ap2 is the most significant bit) when the sign code Ap3 is xe2x80x9c1xe2x80x9d and then to add xe2x80x9c1xe2x80x9d, getting the negative control bits Xp0 to Xp2 from the sum nodes S of the half-adders 39A to 39C and the negative control code Co from the carry node C of the half-adder 39C.
As mentioned above, in the prior art converter 10, when the input code 26 represents a positive value, the sign code Ap3 is xe2x80x9c0xe2x80x9d, the positive control code 28A being equal to the bits Ap2 to Ap0 of the value code 32, the negative control code 28C being xe2x80x9c000xe2x80x9d. The positive current sources of the converter 10 can correctly provide a positive current for generating a positive output voltage Vp according to the input code 26. In the control logic 12, the positive control bits Yp0 to Yp2 of the positive control code 28A are generated by separately calculating the bits Ap0 to Ap2 with the inverter 34 of the bit Ap3. When the bit Ap3 is xe2x80x9c0xe2x80x9d, the positive control code 28A is the same as the value code 32. At the same time, the inputs of the half-adders 39A to 39C connected to the AND gates 36 are provided with the bit Ap3. When the bit Ap3 is xe2x80x9c0xe2x80x9d, the half-adders 39A to 39C add xe2x80x9c0xe2x80x9d to xe2x80x9c000xe2x80x9d in binary, each sum node S and each carry node C being xe2x80x9c0xe2x80x9d, the negative control bits Xp0 to Xp2 and Co being xe2x80x9c0xe2x80x9d, thereby providing a positive output voltage according to the positive value of the input code 26, as shown in FIG. 2.
On the contrary, when the input code 26 represents a negative value by 2s complement, the sign code Ap3 is xe2x80x9c1xe2x80x9d and each bit of the value code 32 is xe2x80x9c0xe2x80x9d, the positive control bits Yp0 to Yp2 being xe2x80x9c0xe2x80x9d. The half-adders 39A to 39C add xe2x80x9c1xe2x80x9d to the inverters of the bits of the value code 32 for generating the negative control bits Xp0 to Xp2. As mentioned above, when the input code represents a negative value by 2s complement, the negative control code 28B is generated by encoding the value code 32 by 2s complement. The inverters of the bits of the value code 32 are the same as the 1s complement of the value code 32. The negative control code 28B is generated by adding xe2x80x9c1xe2x80x9d to 1s complement of the value code 32, the negative control code also being 2s complement of the value code 32. For instance, when the input code 26 represents 6 by xe2x80x9c1010xe2x80x9d, the valued code 32 is xe2x80x9c010xe2x80x9d, inverting xe2x80x9c010xe2x80x9d into xe2x80x9c101xe2x80x9d and then adding 1 to get xe2x80x9c110xe2x80x9d by binary, xe2x80x9c110xe2x80x9d being the negative control code 28B, as shown in FIG. 2.
As mentioned above, modern digital microprocessors represent negative values by 2s complement. Digital-to-analog converters receive 2s complement representations of the input code to generate corresponding negative output voltages. However, the control logic 12 of the converter 10 encodes the value code 32 of the input code 26 as the negative control code 28B by 2s complement, that is, it takes more logic gates to form the half-adders. For one thing, this increases the gate count in the prior art converter, the layout, and the power required. For another, the latter half-adders must wait for the carry nodes C of the former half-adders for calculation, requiring a significant amount of additional of time. Moreover, an inverter 34 comprises two transistors, an AND gate 36 comprises six transistors, and an XOR gate 38 comprises thirty-eight transistors. As shown in FIG. 3, the prior art requires more than ninety-two transistors.
It is obvious that when the prior art converter processes more bits, the control logic needs more transistors. Please refer to FIG. 4. FIG. 4 is a diagram of the prior art converter 40 expanded to N bits. The converter 40 provides an output voltage Vp at the node Nd of the electrical module 44 according to the N bits input code 56. The control logic 42 of the converter 40 generates the negative control bits Xp(0) to Xp(Nxe2x88x921), Co, and the positive control bits Yp(0) to Yp(Nxe2x88x921) according to the bits Ap(0) to Ap(Nxe2x88x921) of the input code 56, Ap(0) and Ap(Nxe2x88x921) respectively being the least and most significant bits. The positive control bits Yp(0) to Yp(Nxe2x88x921) of the positive electrical module 46A respectively correspond to the positive current sources 48 which provide (2^0)I,(2^1)I to (2^(Nxe2x88x922))I positive current to control the switch 22 between the positive current sources and the node Nc. The negative control bits Xp(0) to Xp(Nxe2x88x921) of the negative electrical module 46B correspond to the negative current sources 50 which provide (2^0)I,(2^1)I to (2^(Nxe2x88x922))I positive current to control whether the negative current sources provide current to the node Nc or not. The OP amp 24 provides an output voltage Vp by the current flowing through the resistance Rp.
FIG. 4 also illustrates a common circuit of the control logic 42. Similar to the control logic 12 in FIG. 3, when the most significant bit Ap(Nxe2x88x921) of the input code 56 is xe2x80x9c0xe2x80x9d, the positive control bits Yp(0) to Yp(Nxe2x88x922) are respectively corresponding to Ap(0) to Ap(Nxe2x88x922) through the AND gates 36 (the negative control bits are xe2x80x9c0xe2x80x9d) to control the positive electrical module 46A to provide an output voltage Vp. When the bit Ap(Nxe2x88x921) is xe2x80x9c1xe2x80x9d, the input code 56 represents negative value by 2s complement, the control logic 42 inverting Ap(0) to Ap(Nxe2x88x922) by Nxe2x88x921 inverters, and then respectively inputting them into (Nxe2x88x921) level half-adders 52 to add xe2x80x9c1xe2x80x9d for 2s complement, the negative control bits generated according to the input code 56. The converter 40 provides an output voltage Vp according to the negative control bits (the positive control bits are xe2x80x9c0xe2x80x9d). As shown in the control logic 42 in FIG. 4, it requires more than 30*(Nxe2x88x921)+2 transistors to accomplish this. This increases the layout size and wastes power during operation. Moreover, the Nxe2x88x921 level half-adders increase the delay of the gates and reduces the efficiency of the prior art digital-to-analog converter.
According to the prior art, when the prior art converter controls the negative output voltage generated by the control electrical module, the input code should be encoded by twos complement arithmetic coding for generating a corresponding control code. This requires more logic gates and more complex logical combinations. This also makes the layout of the prior art converter larger, wastes more power, and extends the delay of the gates and lowers the efficiency of the converter.
It is therefore a primary objective of the claimed invention to provide a digital-to-analog converter and related method that can change the relation between each negative control bit and input code by an electrical module with a new current supply structure for simplifying control logic to solve the above-mentioned problems.
According to the claimed invention, an assistant electrical module is provided in addition to the original positive and negative electrical modules. When the input code is 2xe2x80x3s complement, the assistant electrical module provides extra current to change the current provided by the negative electrical module and the control code for controlling the negative electrical module to be different. After changing the method of controlling the negative electrical module by the control code, the corresponding control code is encoded by 1s complement arithmetic coding according the input code. Thus, fewer control logic gates are required in the claimed invention than in the prior art. This reduces the layout of the converter in the claimed invention, reduces power waste and the delay of the gates, and improves the efficiency of the converter.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.